MICRO-49
    				 vDNN: Virtualized Deep Neural Networks for Scalable, Memory-Efficient Neural Network Design
    				Minsoo Rhu, Natalia Gimelshein, Jason Clemons, Arslan Zulfiqar, and Stephen W. Keckler
            The 49th IEEE/ACM International Symposium on Microarchitecture (MICRO-49), Taipei, Taiwan, Oct. 2016
            [PDF]
            [Slide]
            [Code]
    		
         
				HPCA-23
    				 Architecting an Energy-Efficient DRAM System For GPUs
    				Niladrish Chatterjee, Mike O'Connor, Donghyuk Lee, Daniel R. Johnson, Stephen W. Keckler, Minsoo Rhu, and William J. Dally
    				The 23rd IEEE International Symposium on High Performance Computer Architecture (HPCA-23), Austin, TX, Feb. 2017
            [PDF]
    		
         
				MICRO-48
    				 CLEAN-ECC: High Reliability ECC for Adaptive Granularity Memory System
    				Seong-Lyong Gong, Minsoo Rhu, Jungrae Kim, Jinsuk Chung, and Mattan Erez
    				The 48th IEEE/ACM International Symposium on Microarchitecture (MICRO-48), Waikiki, HI, Dec. 2015
            [PDF]
    		
         
				HPCA-21
    				 Priority-Based Cache Allocation for Throughput Processors
    				Dong Li*, Minsoo Rhu, Daniel R. Johnson, Mike O'Connor, Mattan Erez, Doug Burger, Donald S. Fussell, and Stephen W. Keckler
    				The 21st IEEE International Symposium on High Performance Computer Architecture (HPCA-21), San Francisco, CA, Feb. 2015
            *Dong Li is a co-first author of this work.
            [PDF]
            [Slide]
    		
         
				ISLPED'14
    				 GPUVolt: Characterizing and Mitigating Voltage Noise in GPUs
    				Jingwen Leng, Yazhou Zu, Minsoo Rhu, Meeta Sharma Gupta, and Vijay Janapa Reddi
    				The IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED-2014), La Jolla, CA, Aug. 2014
            [PDF]
    		
         
				MICRO-46
    				 A Locality-Aware Memory Hierarchy for Energy-Efficient GPU Architectures
    				Minsoo Rhu, Michael Sullivan, Jingwen Leng, and Mattan Erez
    				The 46th IEEE/ACM International Symposium on Microarchitecture (MICRO-46), Davis, CA, Dec. 2013
            [PDF]
            [Slide]
    		
         
				ISCA-40
    				 Maximizing SIMD Resource Utilization in GPGPUs with SIMD Lane Permutation
    				Minsoo Rhu and Mattan Erez
    				The 40th IEEE/ACM International Symposium on Computer Architecture (ISCA-40), Tel-Aviv, Israel, Jun. 2013
            [PDF]
            [Slide]
    		
         
				HPCA-19
    				 The Dual-Path Execution Model for Efficient GPU Control Flow
    				Minsoo Rhu and Mattan Erez
    				The 19th IEEE International Symposium on High Performance Computer Architecture (HPCA-19), Shenzhen, China, Feb. 2013
            [PDF]
            [Slide]
    		
         
				ISCA-39
    				 CAPRI: Prediction of Compaction-Adequacy for Handling Control-Divergence in GPGPU Architectures
    				Minsoo Rhu and Mattan Erez
    				The 39th IEEE/ACM International Symposium on Computer Architecture (ISCA-39), Portland, OR, Jun. 2012
            [PDF]
            [Slide]
    		
         
				TCSVT
    				 Optimization of Arithmetic Coding for JPEG2000
    				Minsoo Rhu and In-Cheol Park
    				IEEE Transactions on Circuits and System for Video Technology, Vol.20, No.3, pp.446-451, Mar. 2010
            [PDF]
    		
         
				ICIP-2009
    				 Memory-less Bit-Plane Coder Architecture for JPEG2000 with Concurrent Column-Stripe Coding
    				Minsoo Rhu and In-Cheol Park
    				IEEE International Conference on Image Processing 2009 (ICIP 2009), Cairo, Egypt, Nov. 2009
            [PDF]
    		
         
				ICIP-2009
    				 Architecture Design of a High-Performance Dual-Symbol Binary Arithmetic Coder for JPEG2000
    				Minsoo Rhu and In-Cheol Park
    				IEEE International Conference on Image Processing 2009 (ICIP 2009), Cairo, Egypt, Nov. 2009
            [PDF]
    		
         
				SiPS-2009
    				 A Novel Trace-Pipelined Binary Arithmetic Coder Architecture for JPEG2000
    				Minsoo Rhu and In-Cheol Park
    				IEEE Workshop on Signal Processing Systems 2009 (SiPS 2009), Tampere, Finland, Oct. 2009
            [PDF]